Managing Pipeline-Recon gurable FPGAs

While recon gurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to signi cantly reduce both these costs. In this paper we describe the bene ts of hardware virtualization, and show how it can be acheived using a combination of pipeline recon guration and run-time scheduling of both con guration streams and data streams. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis predicts that PipeRench will outperform commercial FPGAs and DSPs in both overall performance and in performance per mm.